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may 2008 rev 4 1/57 1 STA328 2.1-channel high-effici ency digital audio system features ! wide supply voltage range (10 v - 36 v) ! three power output configurations ?2x40w + 1x80w ?2x80w ?1x160w ! powerso-36 package ! 2.1 channels of 24-bit ddx ? ! 100-db snr and dynamic range ! 32 khz to 192 khz input sample rates ! digital gain/attenuation +48 db to -80 db in 0.5-db steps ! four 28-bit user programmable biquads (eq) per channel ! i 2 c control ! 2-channel i 2 s input data interface ! individual channel and master gain/attenuation ! individual channel and master soft/hard mute ! individual channel volume and eq bypass ! bass/treble tone control ! dual independent programmable limiters/compressors ! automodes ? 32 preset eq curves ? 15 preset crossover settings ? auto volume controlled loudness ? 3 preset volume curves ? 2 preset anti-clipping modes ? preset night-time listening mode ? preset tv agc ! input and output channel mapping ! am noise-reduction and pwm frequency-shifting modes ! software volume update and muting ! auto zero detect and invalid input detect muting ! selectable ddx ? ternary or binary pwm output + variable pwm speeds ! selectable de-emphasis ! post-eq user programmable mix with default 2.1 bass-management settings ! variable max power correction for lower full- power thd ! four output routing configurations ! selectable clock input ratio ! 96 khz internal processing sample rate, 24 to 28-bit precision ! video application supports 576 * fs input mode. powerso-36 with slug up table 1. device summary order code package packaging STA328 powerso-36 tube STA32813tr powerso-36 tape and reel www.st.com
contents STA328 2/57 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 eq processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 output configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 package pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 general interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 dc electrical specifications (3.3 v buffers) . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 power electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5i 2 c bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 configuration register a (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 configuration register b (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3 configuration register c (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.1 ddx ? power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.2 ddx ? variable compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4 configuration register d (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5 configuration register e (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STA328 contents 3/57 6.6 configuration register f (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.7 volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.7.1 master controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.7.2 channel controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.7.3 volume description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.8 automode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.8.1 automodes eq, volume, gc (addr 0x0b) . . . . . . . . . . . . . . . . . . . . . . . 35 6.8.2 automode am/pre-scale/bass management scale (addr 0x0c) . . . . . . 36 6.8.3 preset eq settings (addr 0x0d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.9 channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.9.1 channel 1 configuration (addr 0x0e) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.9.2 channel 2 configuration (addr 0x0f) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.9.3 channel 3 configuration (addr 0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.10 tone control (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.11 dynamics control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.11.1 limiter 1 attack/release threshold (addr 0x12) . . . . . . . . . . . . . . . . . . . . 41 6.11.2 limiter 1 attack/release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . . . 41 6.11.3 limiter 2 attack/release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . . 41 6.11.4 limiter 2 attack/release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . . . 41 6.11.5 dynamics control description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.11.6 anti-clipping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.11.7 dynamic range compression mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7 user programmable processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.1 eq - biquad equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2 pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.3 post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.4 mix/bass management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5 calculating 24-bit signed fractional numbers from a db value . . . . . . . . . 47 7.6 user defined coefficient ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.6.1 coefficient address register 1 (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . 47 7.6.2 coefficient b1data register bits 23:16 (addr 0x17) . . . . . . . . . . . . . . . . . 47 7.6.3 coefficient b1data register bits 15:8 (addr 0x18) . . . . . . . . . . . . . . . . . . 47 7.6.4 coefficient b1data register bits 7:0 (addr 0x19) . . . . . . . . . . . . . . . . . . . 47 7.6.5 coefficient b2 data register bits 23:16 (addr 0x1a) . . . . . . . . . . . . . . . . 47 7.6.6 coefficient b2 data register bits 15:8 (addr 0x1b) . . . . . . . . . . . . . . . . . 48
contents STA328 4/57 7.6.7 coefficient b2 data register bits 7:0 (addr 0x1c) . . . . . . . . . . . . . . . . . . 48 7.6.8 coefficient a1 data register bits 23:16 (addr 0x1d) . . . . . . . . . . . . . . . . 48 7.6.9 coefficient a1 data register bits 15:8 (addr 0x1e) . . . . . . . . . . . . . . . . . 48 7.6.10 coefficient a1 data register bits 7:0 (addr 0x1f) . . . . . . . . . . . . . . . . . . 48 7.6.11 coefficient a2 data register bits 23:16 (addr 0x20) . . . . . . . . . . . . . . . . 48 7.6.12 coefficient a2 data register bits 15:8 (addr 0x21) . . . . . . . . . . . . . . . . . 48 7.6.13 coefficient a2 data register bits 7:0 (addr 0x22) . . . . . . . . . . . . . . . . . . 48 7.6.14 coefficient b0 data register bits 23:16 (addr 0x23) . . . . . . . . . . . . . . . . 49 7.6.15 coefficient b0 data register bits 15:8 (addr 0x24) . . . . . . . . . . . . . . . . . 49 7.6.16 coefficient b0 data register bits 7:0 (addr 0x25) . . . . . . . . . . . . . . . . . . 49 7.6.17 coefficient write control register (addr 0x26) . . . . . . . . . . . . . . . . . . . . . 49 7.7 reading a coefficient from ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.8 reading a set of coefficients from ram . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.9 writing a single coefficient to ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.10 writing a set of coefficients to ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.11 variable max power correction (addr 0x27, 0x28) . . . . . . . . . . . . . . . . . . 53 7.12 fault detect recovery (addr 0x2b, 0x2c) . . . . . . . . . . . . . . . . . . . . . . . . . 53 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
STA328 description 5/57 1 description 1.1 overview the STA328 comprises digital audio processing, digital amplifier control and ddx ? power output stage to create a high-power single-chip ddx ? solution for high-quality, high-efficiency, all di gital amplification. the STA328 power section consists of four independent half-bridges. these can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half-bridges and a single full-bridge to give up to 2 x 40 w plus 1 x 80 w of power output. two channels can be provided by two full-bridges to give up to 2 x 80 w of power. the ic can also be configured as a single parallel full-bridge capable of high-current operation and 1 x 160 w output. also provided in the STA328 is a full assortment of digital processing features. this includes up to four programmable 28-bit biquads (eq) per channel and bass/treble tone control. automodes enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. this includes auto volume loudness, preset volume curves, preset eq settings. new advanced am radio-interference reduction modes. the serial audio data input interface accepts all possible formats, including the popular i 2 s format. three channels of ddx ? processing are provided. this high-quality conversion from pcm audio to patented ddx ? 3-state pwm switching provides over 100 db of snr and dynamic range. figure 1. block diagram figure 2. channel signal flow diagram through the digital core serial data input, channel mapping & resampling ddx ? processing quad half-bridge power stage out1a out1b out2a out2b lrcki sdi_12 sda scl pll clk eapd bicki fault twarn power-down i 2 c system contro l audio eq, mix, crossver, volume, limiter processing system timing ddx-spirit serial data input, channel mapping & resampling ddx ? processing quad half-bridge power stage out1a out1b out2a out2b lrcki sdi_12 sda scl pll clk eapd bicki fault twarn power-down i 2 c system contro l audio eq, mix, crossver, volume, limiter processing system timing ddx-spirit channel mapping re-samp ling eq processing mix volume limiter 4x interp ddx ? i 2 s input ddx output crossover filter
description STA328 6/57 1.2 eq processing two channels of input data (re-sampled if necessary) at 96 khz are provided to the eq processing block. in this block, up to four user-defined biquads can be applied to each of the two channels. pre-scaling, dc-blocking, high-pass, de-emphasis, bass, and tone control filters can also be applied based on various configuration parameter settings. the entire eq block can be bypassed for all channels simultaneously by setting the dspb bit to 1. and the cxeqbp bits can be used to bypass the eq function on a per channel basis. figure 3 shows the internal signal flow through the eq block. figure 3. channel signal flow through the eq block 1.3 output configurations figure 4. output power-stage configurations pre scale high-pass filter bq#1 bq#2 bass filter de- emphasis treble filter re-sampled input to mix bq#4 bq#3 if hpb = 0 4 biquads user defined if ameq = 00 preset eq if ameq = 01 auto loudness if ameq = 10 if demp = 1 if cxt cb = 0 bt c: bass boost /cut ttc: treble boost/cut if dspb = 0 & cxeqb = 0 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 2 channel 1 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 2 channel 1 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 3 channel 1 channel 2 2-channel (full-bridge) configuration, register bits ocfg[1:0] = 00 2.1-channel configuration, register bits ocfg[1:0] = 01 1-channel mono-parallel configuration, register bits ocfg[1:0] = 11 the setup register is configuration register f (addr 0x05) on page 31 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 3
STA328 description 7/57 1.4 applications figure 5. application circuit for 2.1/2.0 configurable solution sub_gnd
pin out STA328 8/57 2 pin out 2.1 package pins figure 6. pin connections 2.2 pin list vcc_sign vss vdd gnd bicki lrcki sdi vdda gnda xti pll_filter reserved sda scl reset config vl vdd_reg sub_gnd n.c. out2b vcc2b n.c. gnd2b gnd2a vcc2a out2a out1b vcc1b gnd1b gnd1a n.c. vcc1a out1a gnd_clean gnd_reg 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 table 2. pin list number type name description 1 i/o sub_gnd ground 2 n.c. n.c. not connected 3 o out2b output half bridge 2b 4 i/o vcc2b positive supply 5 n.c. n.c. not connected 6 i/o gnd2b negative supply 7 i/o gnd2a negative supply 8 i/o vcc2a positive supply 9 o out2a output half bridge 2a 10 o out1b output half bridge 1b 11 i/o vcc1b positive supply 12 i/o gnd1b negative supply 13 i/o. gnd1a negative supply 14 n.c. n.c. not connected
STA328 pin out 9/57 2.3 pin description out1a, 1b, 2a and 2b (pins 16, 10, 9 and 3) output half bridge pwm outputs 1a, 1b, 2a and 2b provide the input signals to the speakers. reset (pin 22) driving reset low sets all outputs low and re turns all register settings to their default (reset) values. the reset is asynchronous to the internal clock. 15 i/o vcc1a positive supply 16 o out1a output half bridge 1a 17 i/o gnd_clean logical ground 18 i/o gnd_reg substrate ground 19 i/o vdd_reg logic supply 20 i/o vl logic supply 21 i config logic levels 22 i reset reset 23 i scl i 2 c serial clock 24 i/o sda i 2 c serial data 25 - reserved this pin must be connected to gnd 26 i pll_filter connection to pll filter 27 i xti pll input clock 28 i/o gnda analog ground 29 i/o vdda analog supply, nominally 3.3 v 30 i sdi i 2 s serial data channels 1 & 2 31 i/o lrcki i 2 s left/right clock, 32 i bicki i 2 s serial clock 33 i/o gnd digital ground 34 i/o vdd digital supply, nominally 3.3 v 35 i/o vss 5 v regulator referred to +v cc 36 i/o vcc_sign 5 v regulator referred to ground table 2. pin list number type name description
pin out STA328 10/57 i 2 c signals (pins 23 and 24) the sda (i 2 c data) and scl (i 2 c clock) pins operate according to the i 2 c specification ( chapter 5 on page 16 gives more information). fast-mode (400 kb/s) i 2 c communication is supported. gnda and vdda (pins 28 and 29) this is the 3.3 v analog supply for the phase locked loop. it must be well decoupled and filtered for good noise immunity since the a udio performance of the device depends upon the pll circuit. clk (pin 27) this is the master clock in used by the digital core. the master clock must be an integer multiple of the lr clock frequency. typically, the master clock frequency is 12.288 mhz (256 * fs) for a 48 khz sample rate; it is the default setting at power-up. care must be taken to provide the device with the nominal system clock frequency; over-clocking the device may result in anomalous operation, su ch as inability to communicate. filter_pll (pin 26) this is the connection for external filter components for the pll loop compensation. the schematic diagram in figure 5 on page 7 shows the recommended circuit. bicki (pin 32) the serial or bit clock input is for framing each data bit. the bit clock frequency is typically 64 * fs using i 2 s serial format. sdi_12 (pin 30) this is the serial data input where pcm audio information enters the device. six format choices are available including i 2 s, left or right justified, lsb or msb first, with word widths of 16, 18, 20 and 24 bits. lrcki (pin 31) the left/right clock input is for data word framing. the clock frequency is at the input sample rate, fs.
STA328 electrical specifications 11/57 3 electrical specifications table 3. absolute maximum ratings table 4. thermal data table 5. recommended operating conditions 3.1 general interface specifications operating conditions v dd33 = 3.3 v 0.3 v, t amb = 25 c unless otherwise specified symbol parameter value unit v dd33 3.3 v i/o power supply (pins vdda, vdd) -0.5 to 4 v v i voltage on input pins -0.5 to (v dd33 +0.5) v v o voltage on output pins -0.5 to (v dd33 +0.5) v t stg storage temperature -40 to +150 c t amb ambient operating temperature -20 to +85 c v cc dc supply voltage (pins vccna, vccnb) 40 v v max maximum voltage on vl (pin 20) 5.5 v symbol parameter min typ max unit r thj-case thermal resistance junction to case (thermal pad) 2.5 c/w t j-sd thermal shut-down junction temperature 150 c t warn thermal warning temperature 130 c t h-sd thermal shut-down hysteresis 25 c symbol parameter value unit v dd33 i/o power supply 3.0 to 3.6 v t j operating junction temperature -20 to +125 c table 6. general interface electrical characteristics symbol parameter test condition min. typ. max. unit i il low level input no pull-up v i = 0 v (1) 1. the leakage currents are generally very small (< 1 na). the values given her e are the maximum values after an electrostatic stress on the pin. 1 a i ih high level input no pull-down v i = v dd33 (1) 2 a i oz 3-state output leakage without pull-up/down v i = v dd33 (1) 2 a v esd electrostatic protection (human-body model) leakage current < 1 a2000 v
electrical specifications STA328 12/57 3.2 dc electrical specifications (3.3 v buffers) operating conditions v dd33 = 3.3 v 0.3 v, t amb = 25 c unless otherwise specified 3.3 power electrical specifications operating conditions v dd33 = 3.3 v 0.3 v, v l = 3.3 v, v cc =30v, t amb = 25 c unless otherwise specified. table 7. dc electrical specifications symbol parameter test condition min. typ. max. unit v il low level input voltage 0.8 v v ih high level input voltage 2.0 v v hyst schmitt trigger hysteresis 0.4 v v ol low level output ioi = 2 ma 0.15 v v oh high level output ioh = -2 ma v dd33 - 0.15 v table 8. power electrical characteristics symbol parameter test conditions min. typ. max. unit r dson power pchannel/nchannel mosfet rdson id = 1a 200 270 m ? i dss power pchannel/nchannel leakage idss v cc = 35 v 50 a g n power pchannel rdson matching id = 1 a 95 % g p power nchannel rdson matching id = 1 a 95 % dt_s low current dead time (static) see test circuits, figure 7 and figure 8 10 20 ns t d on turn-on delay time resistive load 100 ns t d off turn-off delay time resistive load 100 ns t r rise time resistive load, figure 7 and figure 8 25 ns t f fall time resistive load, figure 7 and figure 8 25 ns v cc supply voltage 10 36 v v l low logical state voltage vl v l = 3.3 v 0.8 v v h high logical state voltage vh v l = 3.3 v 1.7 v i vcc- pwrdn supply current from v cc in pwrdn pin pwrdn = 0 v 3 ma i vcc-hiz supply current from v cc in 3-state v cc = 30 v, 3-state 22 ma
STA328 electrical specifications 13/57 figure 7. test circuit 1 figure 8. test circuit 2 i vcc supply current from v cc in operation (both channel switching) input pulse width = 50% duty, switching frequency = 384 khz, no lc filters 80 ma i out-sh overcurrent protection threshold (short circuit current limit) 4.5 6 a v uv undervoltage protection threshold 7v t pw-min output minimum pulse width no load 70 150 ns p o output power (refer to test circuit thd = 10% r l = 4 ? , v cc = 21 v r l = 8 ? , v cc = 36 v 50 80 w w p o output power (refer to test circuit thd = 1% r l = 4 ? , v cc = 21 v r l = 8 ? , v cc = 36 v 40 62 w w table 8. power electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit dtr dtf vcc (3/4)vcc (1/2)vcc (1/4)vcc t outxy low current dead time = max(dtr, dtf) +vcc duty cycle = 50% inxy m58 m57 outxy gnd vdc = vcc/2 v67 r 8 w + - high current dead time for bridge application = abs(dtout(a)-dtin(a))+abs(dtout(b)-dtin(b)) +v cc rload=4 ? q2 outb dtout(b) dtin(b) dtout(a) c71 470nf c70 470nf c69 470nf iout=1.5a iout=1.5a q4 q1 q3 m64 inb m63 d06au1651 m58 ina m57 dtin(a) duty cycle=a duty cycle=b duty cycle a and b: fixed to have dc output current of 4a in the direction shown in figure l68 10 l67 10 outa
electrical characteristics curves STA328 14/57 4 electrical characteristics curves figure 9. channel separation vs frequency figure 10. thd vs output power - single ended -90 +10 -80 -70 -60 -50 -40 -30 -20 -10 +0 dbr a 20 20k 50 100 200 500 1k 2k 5k 10k hz -90 +10 -80 -70 -60 -50 -40 -30 -20 -10 +0 dbr a 20 20k 50 100 200 500 1k 2k 5k 10k hz 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 100m 60 200m 500m 1 2 5 10 20 50 thd (%) po (w) vcc = 36 v r l = 4 ? f= 1 khz 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 100m 60 200m 500m 1 2 5 10 20 50 thd (%) po (w) vcc = 36 v r l = 4 ? f= 1 khz
STA328 electrical characteristics curves 15/57 figure 11. thd vs output power - btl figure 12. thd vs frequency - btl 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 100m 100 200m 500m 1 2 5 10 20 50 thd (%) po (w) vcc = 36 v rl = 8 ? f= 1 khz 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 100m 100 200m 500m 1 2 5 10 20 50 thd (%) po (w) vcc = 36 v rl = 8 ? f= 1 khz 0.01 1 0.02 0.05 0.1 0.2 0.5 20 20k 50 100 200 500 1k 2k 5k 10k hz thd (%) vcc = 36 v rl = 8 ? f= 1 khz 0.01 1 0.02 0.05 0.1 0.2 0.5 20 20k 50 100 200 500 1k 2k 5k 10k hz thd (%) vcc = 36 v rl = 8 ? f= 1 khz
i 2 c bus specification STA328 16/57 5 i 2 c bus specification the STA328 supports the i 2 c protocol. this protocol defines any device that sends data on to the i 2 c bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the other as the slave. the master always starts the transfer and provides the serial clock for synchronization. the STA328 is always a slave device in all of its communications. 5.1 communication protocol data transition or change data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high is used to identify a start or stop condition. start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. stop condition stop is identified by a low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communication between STA328 and the bus master. data input during the data input the STA328 samples the sda signal on the rising edge of clock scl. for correct device operation the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low. 5.2 device addressing to start communication between the master and the STA328, the master must initiate with a start condition. following this, the master sends 8 bits (msb first) onto the sda line corresponding to the device select address and read or write mode. the 7 msbs are the device address identifiers, corresponding to the i 2 c bus definition. the STA328 device address is decimal 34 (binary 00100010). the 8th bit (lsb) identifies read or write operation, rw. this bit is set to 1 in read mode and 0 for write mode. after a start condition the STA328 identifies the device address on the bus. if a match is found, it acknowledges the identification on the sda bus during the 9th bit time. the byte following the device identification byte is the internal space address.
STA328 i 2 c bus specification 17/57 5.3 write operation following the start condition the master sends a device select code with the rw bit set to 0. the STA328 acknowledges this and then the master writes the internal address byte. after receiving the internal byte address the STA328 again responds with an acknowledgement. figure 13. i 2 c write procedure byte write in the byte write mode the master sends one data byte. this is acknowledged by the STA328. the master then terminates the transfer by generating a stop condition. multi-byte write the multi-byte write modes can start from any internal address. sequential data byte writes will be written to sequential ad dresses within the STA328. the master generating a stop condition terminates the transfer. 5.4 read operation figure 14. i 2 c read procedure current address byte read following the start condition the master sends a device select code with the rw bit set to 1. the STA328 acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. dev-addr ack start rw sub-addr ack data in a ck stop byte write dev-addr ack start rw sub-addr ack data in a ck stop multibyte write data in a ck dev-addr ack start rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr ack stop random address read data no a ck start rw dev-addr ack start data ack data ack stop sequential current read data no a ck dev-addr ack start rw sub-addr ack dev-addr ack sequential random read data a ck start rw data a ck no a ck stop data rw= high
i 2 c bus specification STA328 18/57 current address multi-byte read the multi-byte read modes can st art from any internal address. sequential data bytes will be read from sequential addresses within the STA328. the master acknowledges each data byte read and then generates a stop condition terminating the transfer. random address byte read following the start condition the master sends a device select code with the rw bit set to 0. the STA328 acknowledges this and then the master writes the internal address byte. after receiving, the internal byte addre ss the STA328 again responds with an acknowledgement. the master then initiates another start condition and sends the device select code with the rw bit set to 1. the STA328 acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. random address multi-byte read the multi-byte read modes could start from an y internal address. s equential data bytes will be read from sequential addresses within the STA328. the master acknowledges each data byte read and then generates a stop condition terminating the transfer.
STA328 register description 19/57 6 register description you must not reprogram the register bits marked ?reserved?. it is important that these bits keep their default reset values. table 9. register summary addressnamed7d6d5d4d3d2 d1 d0 0x00 confa fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 0x01 confb c2im c1im dscke saifb sai3 sai2 sai1 sai0 0x02 confc reserved csz4 csz3 csz2 csz1 csz0 om1 om0 0x03 confd mme zde drc bql psl dspb demp hpb 0x04 confe sve zce reserved pwms ame reserved mpc mpcv 0x05 conff eapd pwdn ecle reserved bcle ide ocfg1 ocfg0 0x06 mmute reserved reserved reserved reserved reserved reserved reserved mmute 0x07 mvol mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 0x08 c1vol c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 0x09 c2vol c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 0x0a c3vol c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 0x0b auto1 amps reserved amgc1 amgc0 amv1 amv0 ameq1 ameq0 0x0c auto2 xo3 xo2 xo1 xo1 amam2 amam1 amam0 amame 0x0d auto3 reserved reserved reserved peq4 peq3 peq2 peq1 peq0 0x0e c1cfg c1om1 c1om0 c1ls1 c1ls0 c1bo c1vbp c1eqbp c1tcb 0x1f c2cfg c2om1 c2om0 c2ls1 c2ls0 c2bo c2vbp c2eqbp c2tcb 0x10 c3cfg c3om1 c3om0 c3ls1 c3ls0 c3bo c3vbp reserved reserved 0x11 tone ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 0x12 l1ar l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 0x13 l1atrt l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 0x14 l2ar l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 0x15 l2atrt l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 0x16 cfaddr2 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 0x17 b1cf1 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 0x18 b1cf2 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 0x19 b1cf3 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 0x1a b2cf1 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 0x1b b2cf2 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 0x1c b2cf3 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 0x1d a1cf1 c3b23 c3b22 c3b21 c3b20 c3b19 c3b18 c3b17 c3b16
register description STA328 20/57 6.1 configuration register a (addr 0x00) the STA328 will support sample rates of 32 khz, 44.1 khz, 48 khz, 88.2 khz, and 96 khz. therefore the internal clock will be: " 32.768 mhz for 32 khz " 45.1584 mhz for 44.1 khz, 88.2 khz, and 176.4 khz " 49.152 mhz for 48 khz, 96 khz, and 192 khz the external clock frequency provided to the xti pin must be a multiple of the input sample frequency (fs). the correlation between the input clock and the input sample rate is determined by the status of the mcsx bits and the ir (input rate) register bits. the mcsx 0x1e a1cf2 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 0x1f a1cf3 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 0x20 a2cf1 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 0x21 a2cf2 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 0x22 a2cf3 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 0x23 b0cf1 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 0x24 b0cf2 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 0x25 b0cf3 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 0x26 cfud reserved reserved reserved reserved ra r1 wa w1 0x27 mpcc1 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 0x28 mpcc2 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 0x29 reserved reserved reserved reserved re served reserved reserved reserved reserved 0x2a reserved reserved reserved reserved re served reserved reserved reserved reserved 0x2b fdrc1 fdrc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 0x2c fdrc2 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 0x2d reserved reserved reserved reserved re served reserved reserved reserved reserved d7 d6 d5 d4 d3 d2 d1 d0 fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 01100011 table 9. register summary addressnamed7d6d5d4d3d2 d1 d0 table 10. master clock select bit r/w rst name description 0rw1mcs0 master clock select : selects the ratio between the input i 2 s sample frequency and the input clock. 1rw1mcs1 2rw0mcs2
STA328 register description 21/57 bits determine the pll factor generating the internal clock and the ir bit determines the oversampling ratio used internally. the STA328 has variable interpolation (re-sampling) settings such that internal processing and ddx ? output rates remain consistent. the first processing block interpolates by either 2 times or 1 time (pass-through) or provides a down-sample by a factor of 2. the ir bits determine the re-sampling ratio of this interpolation. if the thermal warning adjustment is enabled (twab = 0), then the thermal warning recovery will determine if the adjustment is removed when thermal warning is negative. if twrb = 0 and twab = 0, then when a thermal warning disappears the gain adjustment determined by the thermal warning post-scale (default = -3 db) will be removed and the gain will be added back to the system. if twrb = 1 and twab = 0, then when a thermal warning disappears the thermal warnin g post-scale gain adjustment will remain until twrb is changed to zero or the device is reset. table 11. ir and mcs settings for input sample rate and clock rate input sample rate fs (khz) ir mcs[2:0] 000 001 010 011 100 101 32, 44.1, 48 00 768 fs 512 fs 384 fs 256 fs 128 fs 576 fs 88.2, 96 01 384 fs 256 fs 192 fs 128 fs 64 fs x 176.4, 192 1x 384 fs 256 fs 192 fs 128 fs 64 fs x table 12. interpolation ratio select bit r/w rst name description 4:3 rw 00 ir[1:0] interpolation ratio select: selects internal interpolation ratio based on input i 2 s sample frequency table 13. ir bit settings as a function of input sample rate input sample rate fs (khz) ir[1,0] 1 st stage interpolation ratio 32 00 2 times over-sampling 44.1 00 2 times over-sampling 48 00 2 times over-sampling 88.2 01 pass-through 96 01 pass-through 176.4 10 down-sampling by 2 192 10 down-sampling by 2 table 14. thermal warning recovery bypass bit r/w rst name description 5rw1twrb thermal warning recovery bypass: 0: thermal warning recovery enabled 1: thermal warning recovery disabled
register description STA328 22/57 the on-chip STA328 power output block provides feedback to the digital controller using inputs to the power control block. the twarn input is used to indicate a thermal warning condition. when twarn is asserted (set to 0) for a period greater than 400 ms, the power control block will force an adjustment to the mo dulation limit in an a ttempt to eliminate the thermal warning condition. once the therma l warning volume adjustment is applied, whether the gain is reapplied when twarn is de-asserted is dependent on the twrb bit. the ddx ? power block can provide feedback to the digital controller using inputs to the power control block. the fault input is used to indicate a fault condition (either over-current or thermal). when fault is asserted (set to 0), the power control block will attempt a recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power output block to begin recovery). it holds it at 0 for period of time in the range of 0.1 ms to 1 s as defined by the fault-detect recovery constant register (fdrc registers 0x29 to 0x2a), then toggle it back to 1. this sequence is repe ated as log as the fault indication exists. this feature is enabled by default but can be bypassed by setting the fdrb control bit to 1. table 15. thermal warning adjustment bypass bit r/w rst name description 6rw1twab thermal warning adjustment bypass: 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled table 16. fault detect recovery bypass bit r/w rst name description 7rw0fdrb fault detector recovery bypass: 0: fault detector recovery enabled 1: fault detector recovery disabled
STA328 register description 23/57 6.2 configuration register b (addr 0x01) this register configures the serial data interface the STA328 serial audio input was designed to interface with standard digital audio components and to accept a number of serial data formats. the STA328 always acts as a slave when receiving audio input from standard digital audio components. serial data for two channels is provided using 3 input pins: left/right clock lrcki (pin 31), serial clock bicki (pin 32), and serial data sdi (pin 30). sai[3:0] and saifb are used to specify the serial data format. the default format is i 2 s, msb-first. available formats are shown below in figure 15 and the tables that follow. figure 15. general serial input and output formats ta bl e 1 8 lists the serial audio input formats supported by STA328 when bicki = 32 * fs, 48 * fs and 64 * fs, where the sampling rate fs = 32, 44.1, 48, 88.2, 96, 176.4 or 192 khz. d7 d6 d5 d4 d3 d2 d1 d0 c2im c1im dscke saifb sai3 sai2 sai1 sai0 1 0 0 0 0000 table 17. serial audio input interface format bit r/w rst name description 3:0 rw 0000 sai[3:0] serial audio input interface format: determines the interface format of the input serial digital audio interface (see below). 4 rw 0 saifb data format: 0: msb first 1: lsb first i 2 s left justified lrclk left right sclk sdata lsb msb lsb msb msb lrclk left right sclk sdata lsb msb lsb msb msb right justified lrclk left right sclk sdata lsb msb lsb msb msb
register description STA328 24/57 for example, sai = 1110 and saifb = 1 would specify right-justified 16-bit data, lsb-first. table 18. supported serial audio input formats bicki sai [3:0] saifb interface format 32 * fs 1100 x i 2 s 15-bit data 1110 x left/right justified 16-bit data 48 * fs 0100 x i 2 s 23-bit data 0100 x i 2 s 20-bit data 1000 x i 2 s 18-bit data 0100 0 msb first i 2 s 16-bit data 1100 1 lsb first i 2 s 16-bit data 0001 x left-justified 24-bit data 0101 x left-justified 20-bit data 1001 x left-justified 18-bit data 1101 x left-justified 16-bit data 0010 x right-justified 24-bit data 0110 x right-justified 20-bit data 1010 x right-justified 18-bit data 1110 x right-justified 16-bit data 64 * fs 0000 x i 2 s 24-bit data 0100 x i 2 s 20-bit data 1000 x i 2 s 18-bit data 0000 0 msb first i 2 s 16-bit data 1100 1 lsb first i 2 s 16-bit data 0001 x left-justified 24-bit data 0101 x left-justified 20-bit data 1001 x left-justified 18-bit data 1101 x left-justified 16-bit data 0010 x right-justified 24-bit data 0110 x right-justified 20-bit data 1010 x right-justified 18-bit data 1110 x right-justified 16-bit data
STA328 register description 25/57 figure 16. serial input data timing each channel received via i 2 s can be mapped to any internal processing channel via the channel input mapping regi sters. this allows for flexibility in processing. the default settings of these registers map each i 2 s input channel to its corresponding processing channel. table 19. serial input data timing characteristics (fs = 32 to 192 khz) parameter in figure 16 value bicki frequency (slave mode) 12.5 mhz max. bicki pulse width low (t0) (slave mode) 40 ns min. bicki pulse width high (t1) (slave mode) 40 ns min. bicki active to lrcki edge delay (t2) 20 ns min. bicki active to lrcki edge delay (t3) 20 ns min. sdi valid to bicki active setup (t4) 20 ns min. bicki active to sdi hold time (t5) 20 ns min. table 20. delay serial clock enable bit r/w rst name description 5 rw 0 dscke delay serial clock enable: 0: no serial clock delay 1: serial clock delay by 1 core clock cycle to tolerate anomalies in some i 2 s master devices table 21. channel input mapping bit r/w rst name description 6rw0c1im 0: processing channel 1 receives left i 2 s input 1: processing channel 1 receives right i 2 s input 7rw1c2im 0: processing channel 2 receives left i 2 s input 1: processing channel 2 receives right i 2 s input bicki t 0 t1 lrcki t2 t3 sdi t4 t5
register description STA328 26/57 6.3 configuration register c (addr 0x02) 6.3.1 ddx ? power output mode the ddx ? power output mode selects how the ddx ? output timing is configured. different power devices can use different output modes. the recommended use is om = 10. when om = 11 the csz bits determine the size of the ddx ? compensating pulse. 6.3.2 ddx ? variable compensating pulse size the ddx ? variable compensating pulse size is intended to adapt to different power stage ics. contact apogee applications for support when deciding this function. d7 d6 d5 d4 d3 d2 d1 d0 reserved csz4 csz3 csz2 csz1 csz0 om1 om0 0 1000010 table 22. ddx ? power output mode bit r/w rst name description 1:0 rw 10 om[1:0] ddx ? power output mode: selects configuration of ddx ? output. table 23. ddx ? output modes om[1,0] output stage - mode 00 not used 01 not used 10 recommended 11 variable compensation table 24. ddx ? compensating pulse csz[4:0] compensating pulse size 00000 0 clock period compensating pulse size 00001 1 clock period compensating pulse size ?? 10000 16 clock period compensating pulse size ?? 11111 31 clock period compensating pulse size
STA328 register description 27/57 6.4 configuration register d (addr 0x03) the STA328 features an internal digital high-pass filter for the purpose of dc blocking. the purpose of this filter is to prevent dc signals from passing through a ddx ? amplifier. dc signals can cause speaker damage. by setting this bit to 1, the de-emphasis will be implemented on all channels. dspb (dsp bypass, bit d2, cfa) bit must be set to 0 for de-emphasis to function. setting the dspb bit bypasses all the eq an d mixing functionality of the STA328 core. post-scale functionality is an attenuation placed after the volume control and directly before the conversion to pwm. post-scale can also be used to limit the maximum modulation index and therefore the peak cu rrent. a setting of 1 in the psl r egister will result in the use of the value stored in channel 1 post-scale for all three internal channels. d7 d6 d5 d4 d3 d2 d1 d0 mme zde drc bql psl dspb demp hpb 01000 0 0 0 table 25. high-pass filter bypass bit r/w rst name description 0rw0hpb high-pass filter bypass bit. 0: ac coupling high pass filter enabled 1: ac coupling high pass filter disabled table 26. de-emphasis bit r/w rst name description 1rw0demp de-emphasis: 0: no de-emphasis 1: de-emphasis table 27. dsp bypass bit r/w rst name description 2 rw 0 dspb dsp bypass bit: 0: normal operation 1: bypass of eq and mixing functionality table 28. post-scale link bit r/w rst name description 3 rw 0 psl post-scale link: 0: each channel uses individual post-scale value 1: each channel uses channel 1 post-scale value
register description STA328 28/57 for ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient ram space by setting the bql bit to 1. therefore, any eq updates only have to be performed once. both limiters can be used in one of two ways, anti-clipping or dynamic range compression. when used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. in dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level. setting the zde bit enables the zero-detect automatic mute. when zde = 1, the zero detect circuit looks at the input data to each processi ng channel after the channel-mapping block. if any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. table 29. biquad coefficient link bit r/w rst name description 4rw0bql biquad link: 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values table 30. dynamic range compression/anti-clipping bit bit r/w rst name description 5 rw 0 drc dynamic range compression/anti-clipping 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode table 31. zero detect mute enable bit r/w rst name description 6rw1zde zero detect mute enable: setting of 1 enables the automatic zero-detect mute table 32. miami mode enable bit r/w rst name description 7rw0mme miami mode enable: 0: sub mix into left/right disabled 1: sub mix into left/right enabled
STA328 register description 29/57 6.5 configuration register e (addr 0x04) by enabling mpc and setting mpcv = 1, the max power correction becomes variable. by adjusting the mpcc registers (address 0x27, 0x28) it becomes possible to adjust the thd at maximum unclipped power to a lower value for a particular application. setting the mpc bit corrects the ddx ? power device at high power. this mode lowers the thd+n of a full ddx ? system at maximum power output and slightly below. the STA328 features a ddx ? processing mode that minimizes the amount of noise generated in the frequency range of am radio. this mode is intended for use when ddx ? is operating in a device with an active am tuner. the snr of the ddx ? processing is reduced to approximately 83 db in this mode, which is still greater than the snr of am radio. d7 d6 d5 d4 d3 d2 d1 d0 sve zce reserved pwms ame reserved mpc mpcv 110 0 001 0 table 33. max power correction variable bit r/w rst name description 0rw0mpcv max power correction variable: 0: use standard mpc coefficient 1: use mpcc bits for mpc coefficient table 34. max power correction bit r/w rst name description 1rw1mpc max power correction: 0: mpc disabled 1: mpc enabled table 35. am mode enable bit r/w rst name description 3rw0ame am mode enable: 0: normal ddx ? operation. 1: am reduction mode ddx ? operation. table 36. pwm speed mode bit r/w rst name description 4 rw 0 pwms pwm speed selection: normal or odd table 37. pwm output speed selections pwms[1:0] pwm output speed 0 normal speed (384 khz) all channels 1 odd speed (341.3 khz) all channels
register description STA328 30/57 the zce bit enables zero-crossing volume adjustments. when volume is adjusted on digital zero-crossings no clicks will be audible. the STA328 includes a soft vo lume algorithm that will step through the intermediate volume values at a predetermined rate when a volume change occurs. by setting sve = 0 this can be bypassed and volume changes will jump from old to new value directly. this feature is only available if individual channe l volume bypass bit is set to 0. table 38. zero-crossing volume enable bit r/w rst name description 6rw1zce zero-crossing volume enable: 1: volume adjustments will only occur at digital zero- crossings 0: volume adjustments will occur immediately table 39. soft volume update enable bit r/w rst name description 7 rw 1 sve soft volume enable: 1: volume adjustments will use soft volume 0: volume adjustments will occur immediately
STA328 register description 31/57 6.6 configuration register f (addr 0x05) setting the ide bit enables this function, which looks at the input i 2 s data and clocking and will automatically mute all outputs if the signals ar e perceived as invalid. detects loss of input mclk in binary mode and will output 50% duty cycl e to prevent audible artifacts when input clocking is lost. d7 d6 d5 d4 d3 d2 d1 d0 eapd pwdn ecle reserved bcle ide ocfg1 ocfg0 0101110 0 table 40. output configuration selection bit r/w rst name description 1:0 rw 00 ocfg[1:0] output configuration selection 00: 2-channel (full-bridge) power, 1-channel ddx ? is default table 41. output configuration selection ocfg[1:0] output power configuration 00 2 channel (full-bridge) power, 1 channel ddx ? : 1a/1b ? 1a/1b 2a/2b ? 2a/2b 01 2 (half-bridge) and 1 (full-bridge) on-board power: 1a ? 1a binary 2a ? 1b binary 3a/3b ? 2a/2b binary 10 reserved 11 1 channel mono-parallel: 3a ? 1a/1b 3b ? 2a/2b table 42. invalid input detect mute enable bit r/w rst name description 2rw1ide invalid input detect auto-mute enable: 0: disabled 1: enabled table 43. binary clock loss detection enable bit r/w rst name description 3rw1bcle binary output mode clock loss detection enable 0: disabled 1: enabled
register description STA328 32/57 when ecle is active, it issues a power devi ce power down signal (eapd) on clock loss detection. eapd is used to actively power down a connected ddx ? power device. this register has to be written to 1 at start-up to enable the ddx ? power device for normal operation. table 44. auto-eapd on clock loss enable bit r/w rst name description 5rw0ecle auto eapd on clock loss 0: disabled 1: enabled table 45. software power down bit r/w rst name description 6rw1pwdn software power down: 0: power down mode: initiates a power-down sequence which results in a soft mute of all channels and finally asserts eapd circa 260 ms later 1: normal operation table 46. external amplifier power down bit r/w rst name description 7 rw 0 eapd external amplifier power down: 0: external power stage power down active 1: normal operation
STA328 register description 33/57 6.7 volume control 6.7.1 master controls master mute register (addr 0x06) master volume register (addr 0x07) note: value of volume derived from mvol is dependent on amv automode volume settings. 6.7.2 channel controls channel 1 volume (addr 0x08) channel 2 volume (addr 0x09) channel 3 volume (addr 0x0a) 6.7.3 volume description the volume structure of the STA328 consists of individual volume registers for each of the three channels and a master volume register, and individual channel volume trim registers. the channel volume settings are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels. these values are normally set at the initialization of the ic and not changed. the individual channel volumes are adjustable in 0.5-db steps from +48 db to -80 db. the master volume control is normally mapped to the master volume of the system. the values of these two settings are summed to find the actual gain/volume value for any given channel. when set to 1, the master mute will mute all channels, whereas th e individual channel mutes (cxm) will mute only that channel. bo th the master mute and the channel mutes provide a ?soft mute? with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 khz). a ?hard d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved reserved reserved reserved mmute 00000000 d7 d6 d5 d4 d3 d2 d1 d0 mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 11111111 d7 d6 d5 d4 d3 d2 d1 d0 c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 01100000
register description STA328 34/57 mute? can be obtained by programming the value 0xff to any channel volume register or the master volume register. when volume offsets are provided via the master volume register any channel whose total volu me is less than -100 db will be muted. all changes in volume take place at zero-crossings when zce = 1 (configuration register e) on a per channel basis as this creates the smoothest possible volume transitions. when zce = 0, volume updates will occur immediately. the STA328 also features a so ft-volume update function that will ramp the volume between intermediate values when the value is updated, when sve = 1 (configuration register e). this feature can be disabled by setting sve = 0. each channel also contains an individual channel volume bypass. if a particular channel has volume bypassed via the cxvbp = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volu me setting will not affect that channel. also, master soft-mute will not affect the channel if cxvbp = 1. each channel also contains a channel mute. if cxm = 1 a soft mute is performed on that channel table 47. master volume offset as a function of mv[7:0] mv[7:0] volume offset from channel value 00000000 (0x00) 0 db 00000001 (0x01) -0.5 db 00000010 (0x02) -1 db ?? 01001100 (0x4c) -38 db ?? 11111110 (0xfe) -127 db 11111111 (0xff) hard master mute table 48. channel volume as a function of cxv[7:0] cxv[7:0] volume 00000000 (0x00) +48 db 00000001 (0x01) +47.5 db 00000010 (0x02) +47db ?? 01100001 (0x5f) +0.5 db 01100000 (0x60) 0 db 01011111 (0x61) -0.5 db ?? 11111110 (0xfe) -79.5 db 11111111 (0xff) hard channel mute
STA328 register description 35/57 6.8 automode registers 6.8.1 automodes eq, volume, gc (addr 0x0b) by setting ameq to any setting other than 00 enables automode eq where biquads 1-4 are not user programmable. any coefficient settings for these biquads are ignored. also when automode eq is used the pre-scale value for channels 1-2 becomes hard-set to -18 db. d7 d6 d5 d4 d3 d2 d1 d0 amps reserved amgc1 amgc0 amv1 amv0 ameq1 ameq0 10000000 table 49. automode eq ameq[1,0] mode (biquad 1-4) 00 user programmable 01 preset eq - peq bits 10 auto volume controlled loudness curve 11 not used table 50. automode volume amv[1,0] mode (mvol) 00 mvol 0.5 db 256 steps (standard) 01 mvol auto curve 30 steps 10 mvol auto curve 40 steps 11 mvol auto curve 50 steps table 51. automode gain compression/limiters amgc[1:0] mode 00 user programmable gc 01 ac no clipping 10 ac limited clipping (10%) 11 drc nighttime listening mode table 52. amps - automode auto prescale bit r/w rst name description 0 rw 0 amps automode pre-scale 0: -18 db used for pre-scale when ameq neq 00 1: user defined pre-scale when ameq neq 00
register description STA328 36/57 6.8.2 automode am/pre-scale/bas s management scale (addr 0x0c) n when ddx ? is used concurrently with an am radio tuner, it is advisable to use the amam bits to automatically adjust the output pwm switching rate dependent upon the specific radio frequency that the tuner is receiving. the values used in amam are also dependent upon the sample rate determined by the adc used. d7 d6 d5 d4 d3 d2 d1 d0 xo3 xo2 xo1 xo0 amam2 amam1 amam0 amame 00000000 table 53. automode am switching enable bit r/w rst name description 0 rw 0 amame automode am enable 0: switching frequency determined by pwms setting 1: switching frequency determined by amam settings 3:1 rw 000 amam[2:0] am switching frequency setting default: 000 table 54. automode am switching frequency selection amam[2:0] 48 khz/96 khz input fs 44.1 khz/88.2 khz input fs 000 0.535 mhz -0.720 mhz 0.535 mhz -0.670 mhz 001 0.721 mhz -0.900 mhz 0.671 mhz -0.800 mhz 010 0.901 mhz -1.100 mhz 0.801 mhz -1.000 mhz 011 1.101 mhz -1.300 mhz 1.001 mhz -1.180 mhz 100 1.301 mhz -1.480 mhz 1.181 mhz -1.340 mhz 101 1.481 mhz -1.600 mhz 1.341 mhz -1.500 mhz 110 1.601 mhz -1.700 mhz 1.501 mhz - 1.700 mhz table 55. automode crossover setting bit r/w rst name description 7:4 rw 0 xo[3:0] automode crossover frequency selection 000: user defined crossover coefficients are used otherwise: preset coefficients for the crossover setting desired table 56. crossover frequency selection xo[2:0] bass management - crossover frequency 0000 user 0001 80 hz 0010 100 hz 0011 120 hz 0100 140 hz
STA328 register description 37/57 6.8.3 preset eq settings (addr 0x0d) 0101 160 hz 0110 180 hz 0111 200 hz 1000 220 hz 1001 240 hz 1010 260 hz 1011 280 hz 1100 300 hz 1101 320 hz 1110 340 hz 1111 360 hz table 56. crossover frequency selection (continued) xo[2:0] bass management - crossover frequency d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved peq4 peq3 peq2 peq1 peq0 00000000 table 57. preset eq selection peq[3:0] setting 00000 flat 00001 rock 00010 soft rock 00011 jazz 00100 classical 00101 dance 00110 pop 00111 soft 01000 hard 01001 party 01010 vocal 01011 hip-hop 01100 dialog 01101 bass-boost #1 01110 bass-boost #2 01111 bass-boost #3 10000 loudness 1 (least boost)
register description STA328 38/57 6.9 channel configuration registers 6.9.1 channel 1 configuration (addr 0x0e) 6.9.2 channel 2 configuration (addr 0x0f) 6.9.3 channel 3 configuration (addr 0x10) eq control can be bypassed on a per channel basis. if eq control is bypassed on a given channel the prescale and all 9 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combination) are bypassed for that channel. 10001 loudness 2 10010 loudness 3 10011 loudness 4 10100 loudness 5 10101 loudness 6 10110 loudness 7 10111 loudness 8 11000 loudness 9 11001 loudness 10 11010 loudness 11 11011 loudness 12 11100 loudness 13 11101 loudness 14 11110 loudness 15 11111 loudness 16 (most boost) table 57. preset eq selection (continued) peq[3:0] setting d7 d6 d5 d4 d3 d2 d1 d0 c1om1 c1om0 c1ls1 c1ls0 c1bo c1vbp c1eqbp c1tcb 000000 00 d7 d6 d5 d4 d3 d2 d1 d0 c2om1 c2om0 c2ls1 c2ls0 c2bo c2vbp c2eqbp c2tcb 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3om1 c3om0 c3ls1 c3ls0 c3bo c3vbp reserved reserved 00000000
STA328 register description 39/57 cxeqbp: " 0 perform eq on channel x - normal operation " 1 bypass eq on channel x tone control (bass/treble) can be bypassed on a per channel basis. if tone control is bypassed on a given channel the two filter s that tone control utilizes are bypassed. cxtcb: " 0 perform tone control on channel x - (default operation) " 1 bypass tone control on channel x each channel can be configured to output either the patented ddx ? pwm data or standard binary pwm encoded data. by setting the cxbo bit to 1, each channel can be individually controlled to be in binary operation mode. also, there is the capability to map each channe l independently onto an y of the two limiters available within the STA328 or even not map it to any limiter at all (default mode). each pwm output channel can receive data from any c hannel output of the volume block. which channel a partic- ular pwm output receives is dependent upon that channel?s cxom register bits. table 58. channel limiter mapping selection cxls[1,0] channel limiter mapping 00 channel has limiting disabled 01 channel is mapped to limiter #1 10 channel is mapped to limiter #2 table 59. channel pwm output mapping cxom[1:0] pwm output from 00 channel 1 01 channel 2 10 channel 3 11 not used
register description STA328 40/57 6.10 tone control (addr 0x11) d7 d6 d5 d4 d3 d2 d1 d0 ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 01110111 table 60. tone control boost/cut selection btc[3:0]/ttc[3:0] boost/cut 0000 -12 db 0001 -12 db ?? 0111 -4 db 0110 -2 db 0111 0 db 1000 +2 db 1001 +4 db ?? 1101 +12 db 1110 +12 db 1111 +12 db
STA328 register description 41/57 6.11 dynamics control 6.11.1 limiter 1 attack/r elease threshold (addr 0x12) 6.11.2 limiter 1 attack/r elease threshold (addr 0x13) 6.11.3 limiter 2 attack/release rate (addr 0x14) 6.11.4 limiter 2 attack/r elease threshold (addr 0x15) 6.11.5 dynamics control description the STA328 includes 2 independent limiter blocks. the purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode, or to actively reduce the dynamic range for a better listening environment (such as a night-time listening mode, which is often needed for dvds.) the two modes are selected via the drc bit in configuration register d (bit 5, address 0x03). each channel can be mapped to limiter1, limiter2, or not mapped. if a channel is not mapped, that channel will c lip normally when 0 dbfs is exceeded. each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then if needed adjust the gain of the mapped channels in unison. the limiter attack thresholds are determined by the lxat registers. when the attack threshold has been exceeded, the limiter, when active, will automatically start reducing the gain. the rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. the gain reduction occurs on a peak-detect algorithm. the release of limiter, when the gain is again increased, is dependent on a rms-detect algorithm. the output of the volume/limiter block is passed through an rms filter. the output of this filter is compared to the release threshold, determined by the release threshold register. when the rms filter output falls below the release threshold, the gain is increased at a rate dependent upon the release rate register. the gain can never be increased past its set value d7 d6 d5 d4 d3 d2 d1 d0 l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 01101010 d7 d6 d5 d4 d3 d2 d1 d0 l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 01101 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 01101010 d7 d6 d5 d4 d3 d2 d1 d0 l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 01101 0 0 1
register description STA328 42/57 and therefore the release will only occur if the limiter has already reduced the gain. the release threshold value can be used to set wh at is effectively a minimum dynamic range. this is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound ?lifeless?. in ac mode the attack and release thresholds are set relative to full-scale. in drc mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. figure 17. basic limiter and volume flow diagram table 61. limiter attack/release rate selection lxa[3:0] attack rate db/ms lxr[3:0] release rate db/ms 0000 3.1584 fast 0000 0.5116 0001 2.7072 0001 0.1370 0010 2.2560 0010 0.0744 0011 1.8048 0011 0.0499 0100 1.3536 0100 0.0360 0101 0.9024 0101 0.0299 0110 0.4512 0110 0.0264 0111 0.2256 0111 0.0208 1000 0.1504 1000 0.0198 1001 0.1123 1001 0.0172 1010 0.0902 1010 0.0147 1011 0.0752 1011 0.0137 1100 0.0645 1100 0.0134 1101 0.0564 1101 0.0117 1110 0.0501 1110 0.0110 1111 0.0451 slow 1111 0.0104 gain attenuation saturation rms limiter gain/volume input output
STA328 register description 43/57 6.11.6 anti-clipping mode table 62. limiter attack/release threshold selection (ac mode) lxat[3:0] attack threshold (ac) db relative to fs lxrt[3:0] release threshold (ac) db relative to fs 0000 -12 0000 - 0001 -10 0001 -29 db 0010 -8 0010 -20 db 0011 -6 0011 -16 db 0100 -4 0100 -14 db 0101 -2 0101 -12 db 0110 0 0110 -10 db 0111 +2 0111 -8 db 1000 +3 1000 -7 db 1001 +4 1001 -6 db 1010 +5 1010 -5 db 1011 +6 1011 -4 db 1100 +7 1100 -3 db 1101 +8 1101 -2 db 1110 +9 1110 -1 db 1111 +10 1111 -0 db
register description STA328 44/57 6.11.7 dynamic range compression mode table 63. limiter attack/release threshold selection (drc mode) lxat[3:0] attack threshold (drc) db relative to volume lxrt[3:0] release threshold (drc) db relative to volume + lxat 0000 -31 0000 - 0001 -29 0001 -38 db 0010 -27 0010 -36 db 0011 -25 0011 -33 db 0100 -23 0100 -31 db 0101 -21 0101 -30 db 0110 -19 0110 -28 db 0111 -17 0111 -26 db 1000 -16 1000 -24 db 1001 -15 1001 -22 db 1010 -14 1010 -20 db 1011 -13 1011 -18 db 1100 -12 1100 -15 db 1101 -10 1101 -12 db 1110 -7 1110 -9 db 1111 -4 1111 -6 db
STA328 user programmable processing 45/57 7 user programmable processing 7.1 eq - biquad equation the biquads use the equation that follows. this is diagrammed in figure 18 below. y[n] = 2(b0/2)x[n] + 2(b1/2)x[n - 1] + b2x[n - 2] - 2(a1/2)y[n - 1] - a2y[n - 2] = b0x[n] + b1x[n - 1] + b2x[n - 2] - a1y[n - 1] - a2y[n - 2] where y[n] represents the output and x[n] represents the input. multipliers are 28-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7fffff (0.9999998808). coefficients stored in the user defined coe fficient ram are referenced in the following manner: " cxhy0 = b1/2 " cxhy1 = b2 " cxhy2 = -a1/2 " cxhy3 = -a2 " cxhy4 = b0/2 the x represents the channel and the y the biquad number. for example c3h41 is the b0/2 coefficient in the fourth biquad for channel 3 figure 18. biquad filter 7.2 pre-scale the pre-scale block which precedes the first biqu ad is used for attenuation when filters are designed that boost frequencies above 0 dbfs. this is a single 28-bit signed multiplier, with 0x800000 = -1 and 0x7fffff = 0.9999998808. by default, all pre-scale factors are set to 0x7fffff. 7.3 post-scale the STA328 provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. this is a 24-bit signed fractional multiplier. the scale factor for this multip lier is loaded into ram using the same i 2 c registers as the biquad coefficients and the mix. all cha nnels can use the same settings as channel 1 by setting the po st-scale link bit. + + + 2 2 -a 2 -a 1 /2 b 2 b 1 /2 b 0 /2 z -1 z -1 z -1 z -1 2
user programmable processing STA328 46/57 7.4 mix/bass management the STA328 provides a post-eq mixing block per channel. each channel has 2 mixing coefficients, which are each 24-bit signed fractional multipliers, that correspond to the 2 channels of input to the mixing block. th ese coefficients are accessible via the user controlled coefficient ram described below. th e mix coefficients are expressed as 24-bit signed; fractional numbers in the range +1.0 (8388607) to -1.0 (-8388608) are used to provide three channels of output from two channels of filtered input. figure 19. mix/bass management block diagram after a mix is achieved, STA328 also provides the capability to implem ent crossover filters on all channels corresponding to 2.1 bass management solution. channels 1 and 2 use a first-order high-pass filter and channel 3 uses a second-order low-pass filter corresponding to the setting of the xo bits of i 2 c register 0x0c. if xo = 000, user specified crossover filters are used. by default these coefficients correspond to pass-through. however, the user can write these coefficients in a similar way as the eq biquads. when user-defined setting is selected, the user can only write 2nd order crossover filters. this output is then passed on to the volume/limiter block. c1mx1 c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 high-pas s xo filter high-pas s xo filter low -pass xo filter user-defined mix coefficients crossover frequency determined by xo setting. user-defined when xo = 000 channel #1 from eq channel #2 from eq channel#1 to gc/vol channel#2 to gc/vol channel#3 to gc/vol + + +
STA328 user programmable processing 47/57 7.5 calculating 24-bit signed fr actional numbers from a db value the pre-scale, mixing, and post-scale functions of the STA328 use 24-bit signed fractional multipliers to attenuate signals. these attenuations can also invert the phase and therefore range in value from -1 to +1. it is possible to calculate the coefficient to utilize for a given negative db value (attenuation) via the equations below. " non-inverting phase numbers 0 to +1: " coefficient = round(8388607 * 10 (db / 20) ) " inverting phase numbers 0 to -1: " coefficient = 16777216 - round(8388607 * 10 (db / 20) ) as can be seen by the preceding equations, the value for positive phase 0 db is 0x7fffff and the value for negative phase 0 db is 0x800000. 7.6 user defined coefficient ram 7.6.1 coefficient addre ss register 1 (addr 0x16) 7.6.2 coefficient b1data r egister bits 23:16 (addr 0x17) 7.6.3 coefficient b1data r egister bits 15:8 (addr 0x18) 7.6.4 coefficient b1data r egister bits 7:0 (addr 0x19) 7.6.5 coefficient b2 data regist er bits 23:16 (addr 0x1a) d7 d6 d5 d4 d3 d2 d1 d0 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 00000000
user programmable processing STA328 48/57 7.6.6 coefficient b2 data regist er bits 15:8 (addr 0x1b) 7.6.7 coefficient b2 data regi ster bits 7:0 (addr 0x1c) 7.6.8 coefficient a1 data regist er bits 23:16 (addr 0x1d) 7.6.9 coefficient a1 data regist er bits 15:8 (addr 0x1e) 7.6.10 coefficient a1 data re gister bits 7:0 (addr 0x1f) 7.6.11 coefficient a2 data register bits 23:16 (addr 0x20) 7.6.12 coefficient a2 data register bits 15:8 (addr 0x21) 7.6.13 coefficient a2 data register bits 7:0 (addr 0x22) d7 d6 d5 d4 d3 d2 d1 d0 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 00000000
STA328 user programmable processing 49/57 7.6.14 coefficient b0 data register bits 23:16 (addr 0x23) 7.6.15 coefficient b0 data register bits 15:8 (addr 0x24) 7.6.16 coefficient b0 data re gister bits 7:0 (addr 0x25) 7.6.17 coefficient write co ntrol register (addr 0x26) coefficients for eq, mix and scaling are handled internally in the STA328 via ram. access to this ram is available to the user via an i 2 c register interface. a collection of i 2 c registers are dedicated to this function. first register c ontains the coefficient base address, five sets of three registers store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the read or write of the coefficient (s) to ram. the following are instructions for re ading and writing coefficients. d7 d6 d5 d4 d3 d2 d1 d0 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved ra r1 wa w1 00000000
user programmable processing STA328 50/57 7.7 reading a coefficient from ram " write 8 bits of address to i 2 c register 0x16 " write 1 to bit r1 (d2) of i 2 c register 0x26 " read top 8 bits of coefficient in i 2 c address 0x17 " read middle 8 bits of coefficient in i 2 c address 0x18 " read bottom 8 bits of coefficient in i 2 c address 0x19 7.8 reading a set of coefficients from ram " write 8 bits of address to i 2 c register 0x16 " write 1 to bit ra (d3) of i 2 c register 0x26 " read top 8 bits of coefficient in i 2 c address 0x17 " read middle 8 bits of coefficient in i 2 c address 0x18 " read bottom 8 bits of coefficient in i 2 c address 0x19 " read top 8 bits of coefficient b2 in i 2 c address 0x1a " read middle 8 bits of coefficient b2 in i 2 c address 0x1b " read bottom 8 bits of coefficient b2 in i 2 c address 0x1c " read top 8 bits of coefficient a1 in i 2 c address 0x1d " read middle 8 bits of coefficient a1 in i 2 c address 0x1e " read bottom 8 bits of coefficient a1 in i 2 c address 0x1f " read top 8 bits of coefficient a2 in i 2 c address 0x20 " read middle 8 bits of coefficient a2 in i 2 c address 0x21 " read bottom 8 bits of coefficient a2 in i 2 c address 0x22 " read top 8 bits of coefficient b0 in i 2 c address 0x23 " read middle 8 bits of coefficient b0 in i 2 c address 0x24 " read bottom 8 bits of coefficient b0 in i 2 c address 0x25 7.9 writing a single coefficient to ram " write 8 bits of address to i 2 c register 0x16 " write top 8 bits of coefficient in i 2 c address 0x17 " write middle 8 bits of coefficient in i 2 c address 0x18 " write bottom 8 bits of coefficient in i 2 c address 0x19 " write 1 to w1 bit in i 2 c address 0x26
STA328 user programmable processing 51/57 7.10 writing a set of coefficients to ram " write 8 bits of starting address to i 2 c register 0x16 " write top 8 bits of coefficient b1 in i 2 c address 0x17 " write middle 8 bits of coefficient b1 in i 2 c address 0x18 " write bottom 8 bits of coefficient b1 in i 2 c address 0x19 " write top 8 bits of coefficient b2 in i 2 c address 0x1a " write middle 8 bits of coefficient b2 in i 2 c address 0x1b " write bottom 8 bits of coefficient b2 in i 2 c address 0x1c " write top 8 bits of coefficient a1 in i 2 c address 0x1d " write middle 8 bits of coefficient a1 in i 2 c address 0x1e " write bottom 8 bits of coefficient a1 in i 2 c address 0x1f " write top 8 bits of coefficient a2 in i 2 c address 0x20 " write middle 8 bits of coefficient a2 in i 2 c address 0x21 " write bottom 8 bits of coefficient a2 in i 2 c address 0x22 " write top 8 bits of coefficient b0 in i 2 c address 0x23 " write middle 8 bits of coefficient b0 in i 2 c address 0x24 " write bottom 8 bits of coefficient b0 in i 2 c address 0x25 " write 1 to wa bit in i 2 c address 0x26 the mechanism for writing a set of coefficients to ram provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. when usi ng this technique, the 8-bit address would specify the address of the biquad b1 coefficient (for example 0, 5, 10, 15, ?, 45 decimal), and the STA328 will generate the ram addresses as offsets from this base value to write the complete set of coefficient data. table 64. ram block for biquads, mixing, and scaling index (decimal) index (hex) coefficient default 0 0x00 channel 1 - biquad 1 c1h10 (b1/2) 0x000000 1 0x01 c1h11 (b2) 0x000000 2 0x02 c1h12 (a1/2) 0x000000 3 0x03 c1h13 (a2) 0x000000 4 0x04 c1h14 (b0/2) 0x400000 5 0x05 channel 1 - biquad 2 c1h20 0x000000 ??? ?? 19 0x13 channel 1 - biquad 4 c1h44 0x400000 20 0x14 channel 2 - biquad 1 c2h10 0x000000 21 0x15 c2h11 0x000000 ??? ?? 39 0x27 channel 2 - biquad 4 c2h44 0x400000
user programmable processing STA328 52/57 40 0x28 high-pass 2 nd order filter for xo = 000 c12h0 (b1/2) 0x000000 41 0x29 c12h1 (b2) 0x000000 42 0x2a c12h2 (a1/2) 0x000000 43 0x2b c12h3 (a2) 0x000000 44 0x2c c12h4 (b0/2) 0x400000 45 0x2d low-pass 2 nd order filter for xo = 000 c12l0 (b1/2) 0x000000 46 0x2e c12l1 (b2) 0x000000 47 0x2f c12l2 (a1/2) 0x000000 48 0x30 c12l3 (a2) 0x000000 49 0x31 c12l4 (b0/2) 0x400000 50 0x32 channel 1 - pre-scale c1pres 0x7fffff 51 0x33 channel 2 - pre-scale c2pres 0x7fffff 52 0x34 channel 1 - post-scale c1psts 0x7fffff 53 0x35 channel 2 - post-scale c2psts 0x7fffff 54 0x36 channel 3 - post-scale c3psts 0x7fffff 55 0x37 thermal warning - post scale twpsts 0x5a9df7 56 0x38 channel 1 - mix 1 c1mx1 0x7fffff 57 0x39 channel 1 - mix 2 c1mx2 0x000000 58 0x3a channel 2 - mix 1 c2mx1 0x000000 59 0x3b channel 2 - mix 2 c2mx2 0x7fffff 60 0x3c channel 3 - mix 1 c3mx1 0x400000 61 0x3d channel 3 - mix 2 c3mx2 0x400000 62 0x3e unused 63 0x3f unused table 64. ram block for biquads, mixing, and scaling (continued) index (decimal) index (hex) coefficient default
STA328 user programmable processing 53/57 7.11 variable max power correction (addr 0x27, 0x28) mpcc bits determine the 16 msbs of the mpc co mpensation coefficient. this coefficient is used in place of the default coefficient when mpcv = 1. 7.12 fault detect recovery (addr 0x2b, 0x2c) fdrc bits specify the 16-bit faul t detect recovery time delay. when fault is asserted, the output tristate will be immediately asserted lo w and held low for the time period specified by this constant. a constant value of 0x0001 in this register is approximately 0.083 ms. the default value of 0x000c specifies approximately 1 ms. d7 d6 d5 d4 d3 d2 d1 d0 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 00101101 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 11000000 d7 d6 d5 d4 d3 d2 d1 d0 frdc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 00000000 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 00001100
package mechanical data STA328 54/57 8 package mechanical data figure 20. powerso-36 slug up outline drawing
STA328 package mechanical data 55/57 in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. table 65. powerso-36 slug up dimensions symbol mm inch min typ max min typ max a 3.25 - 3.43 0.128 - 0.135 a2 3.10 - 3.20 0.122 - 0.126 a4 0.80 - 1.00 0.031 - 0.039 a5-0.20- -0.008- a1 0.03 - -0.04 0.001 - -0.002 b 0.22 - 0.38 0.009 - 0.015 c 0.23 - 0.32 0.009 - 0.013 d 15.80 - 16.00 0.622 - 0.630 d1 9.40 - 9.80 0.370 - 0.386 d2-1.00- -0.039- e 13.90 - 14.50 0.547 - 0.571 e1 10.90 - 11.10 0.429 - 0.437 e2--2.90--0.114 e3 5.80 - 6.20 0.228 - 0.244 e4 2.90 - 3.20 0.114 - 0.126 e - 0.65 - - 0.026 - e3 - 11.05 - - 0.435 - g0-0.080-0.003 h 15.50 - 15.90 0.610 - 0.626 h--1.10--0.043 l 0.80 - 1.10 0.031 - 0.043 m 2.25 - 2.60 0.089 - 0.102 n - - 10 degrees - - 10 degrees r- 0.6 - - 0.024- s--8 degrees--8 degrees
revision history STA328 56/57 9 revision history table 66. document revision history date revision changes sep-2004 1 initial release jul-2005 2 added pins 7 and 25 in block diagram may-2006 3 changed from product preview to maturity 13-may-2008 4 updated device pin 1 labeling and connections updated applications schematic figure 5 on page 7 added characterization curves in chapter 4 on page 14 updated device address in section 5.2 on page 16 updated configuration registers in table 9: register summary on page 19 updated configuration registers from section 6.1 on page 20 to section 6.5 updated powerso-36 package mechanical data on page 54
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